// +FHDR------------------------------------------------------------
//                 Copyright (c) 2023 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : dual_port_ram.v
// Author        : ICer
// Created On    : 2023-12-28 18:13
// Last Modified : 2023-12-28 18:14 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------

module dual_port_ram #(
  parameter DEPTH = 16,
  parameter WIDTH = 8)
(
  input wclk    ,
  input wenc    ,
  input [$clog2(DEPTH)-1:0] waddr       ,
  input [WIDTH-1:0] wdata       ,
  input rclk    ,
  input renc    ,
  input [$clog2(DEPTH)-1:0] raddr       ,
  output reg [WIDTH-1:0] rdata
);
 
reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];
 
always @(posedge wclk) begin
  if(wenc)
    RAM_MEM[waddr] <= wdata;
end 
 
always @(posedge rclk) begin
  if(renc)
    rdata <= RAM_MEM[raddr];
end 
 
endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

